IBIS Macromodel Task Group

Meeting date: 02 December 2014

Members (asterisk for those attending):
Altera:                       David Banas
ANSYS:                      * Dan Dvorscak
                            * Curtis Clark
Avago (LSI)                   Xingdong Dai
Cadence Design Systems:     * Ambrish Varma
                              Brad Brim
                              Kumar Keshavan
                              Ken Willis
Ericsson:                     Anders Ekholm
IBM                           Steve Parker
Intel:                      * Michael Mirmak
Keysight Technologies:        Fangyi Rao
                            * Radek Biernacki
Maxim Integrated Products:    Hassan Rafat
Mentor Graphics:            * John Angulo
                            * Arpad Muranyi
Micron Technology:          * Randy Wolff
                              Justin Butterfield
QLogic Corp.                  James Zhou
                              Andy Joy
eASIC                         Marc Kowalski
SiSoft:                     * Walter Katz
                            * Todd Westerhoff
                            * Mike LaBonte
Synopsys                      Rita Horner
Teraspeed Consulting Group:   Scott McMorrow
Teraspeed Labs:             * Bob Ross

(Note: Agilent has changed to Keysight)

The meeting was led by Arpad Muranyi.

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Opens:

- Arpad reviewed our upcoming meeting schedule.


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Call for patent disclosure:

- None


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Review of ARs:

- Todd produce slides for co-optimization requirements discussion.
  - Hoping to show something Dec 9.

- Arpad to review IBIS spec for min max issues.
  - In progress.


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New Discussion:

C_comp:

- Walter showed "C_comp Model Using IBIS-ISS BIRD draft 3"

- Walter showed How to "Measure" VT Curves When Simulating
- slide 3:
  - Walter: The key is knowing how to measure V-T curves.
    - The package and test fixture have RLC elements.
    - IBIS has a note discouraging use of *_dut elements.
    - C_comp is referenced to Pulldown_Ref
  - Arpad: There are new C_Comp_* keywords that use separate references.
- slide 5:
  - Walter: A shunt C_comp Model would have 3 ports: PU_ref, PD_Ref, and pad
- slide 6:
  - Walter: A series model would have four ports, adding a buffer output terminal.
- slide 8:
  - Walter: At the interconnect meeting we said V-T should be measured at B element output, not die pad.
  - Arpad: This should be called an on-die interconnect model, not on-die package.
    - Also "B Element" should be "[Model]"
  - Bob: Are K-T tables compensated for C_comp?
  - Walter: The K-T curves are such that the [Model] output will match test fixture input.
  - Bob: The test fixtures can be vendor specific.
  - Radek: Often C_comp is measured directly at the model terminal.
  - Bob: This contrasts with Randy's slides.

- Walter showed Randy's "C_comp Model Figures".
- slide 3:
  - Walter: This has four ports, we would support this.
- slide 5:
  - Walter: The compensation point is the same.
  - Bob: This has the V-T table prior to C_comp.
  - Arpad: Walter has the same.
  - Radek: I don't like talking about compensation, rather just the measurement point.

- Back to Walter's presentation:
- slide 2:
  - Walter: The description depends on whether on-die interconnect is present.
  - Arpad: IBIS started with the idea that lab measurements could be used to make models.
    - This precludes that because an inaccessible measurement point is used.
  - Walter: De-embedding can be used.
  - Radek: De-embedding could go all the way into the buffer.
  - Bob: C_comp includes device capacitances.
    - De-embedding could eliminate all capacitance.
  - Radek: Sometimes users play with C_comp values.
    - Large values change the time constant, can produce nonsense.
  - Walter: We also have C_comp corners not correlated to V-T corners.
    - This will provide a better definition.
  - Arpad: We viewed C-comp to include all metals.
    - The silicon and metal can vary independently, so we made C_comp independent.
  - Walter: Interconnect capacitance can be lumped in unless there is an on-die model.
  - Arpad: In which cases do corners have to be tied together?
  - Bob: Agree with Walter that C_comp is correlated to model corner.
    - The parameters will modify the calculated V-T waveform.
    - The DUT elements represent easily created SPICE models.
  - John: DUT stands for Don't Use This.

  - Michael M: Is this saying the interconnect corner can differ from the buffer?
  - Arpad: We concluded long ago these could be independent.
  - Michael M: We are trying hard to preserve [Model] as having certain attributes.
    - What is the best way to split it up?
    - It was hard to create an IBIS model for a SATA buffer because of a trench resistor.
    - Trench depth controlled resistance, was orthogonal to other parameters.
    - This was hard to model in IBIS.
    - Where does that resistor fit in?
    - We created a 9 corner model.
    - We need to get beyond 3 corners.
  - Arpad: Can each case be described correctly?
  - Michael M: The resistance in this case is part of the buffer.
    - We have to be careful about defining what goes in the I-V curves.
  - Arpad: It can be hard to simulate all these cases where only some are valid.
  - Michael M: Where should that resistor go?
  - Arpad: There should be no limit on how many series subckts we allow.
  - Radek: The on-die model should be connected to how many reference nodes?
  - Arpad: Probably a total of four nodes.

  - Radek: It is a good solution to have thus IBIS-ISS C_comp model not connected outside the buffer.
  - Bob: It should include series resistance, but that would have to be de-embedded.
  - Walter: We seem to be in agreement.

- Walter showed [C_comp Model] examples.
- Arpad: This looks similar to [External Model].
  - We need to get away from 1-terminal subckts.
  - We have reserved words already for the terminal names.
- Walter: In these names _I stands for inside nodes.

AR: Walter send updated C_comp Model BIRD draft to Mike for posting.

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IBIS Interconnect SPICE Wish List:

1) Simulator directives
